VHDL Tutorial 18: Design a T flip-flop (with enable and an active high reset input) using VHDL

Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial.

In the previous tutorial, VHDL tutorial – 17, we designed a JK flip-flop circuit by using VHDL.

For this project, we will:

Write a VHDL program to build the T flip-flop circuit
Verify the output waveform of the program (the digital circuit) with the flip-flop’s truth table

The T flip-flop with an enable and active high reset input circuit:

Truth table

Note 1: when T=1, the Q output toggles every time (from 0 to 1 and 1 to 0)
Note 2: when T=0, the Q output retains its previous state

Now, let’s write, compile, and simulate a VHDL program. Then, we’ll get the output in waveform and verify it with the given truth table.

Before starting, be sure to review the step-by-step procedure provided in VHDL Tutorial – 3 to design the project. It will ensure that you properly edit and compile the program and the waveform file, including the final output.

Here. we’ve used a behavioral modeling style to write the VHDL program and build this flip-flop circuit because it’s the model preferred for sequential digital circuits.

VHDL program

library ieee;
use ieee.std_logic_1164.all;
entity T_flip_flop is
port (clk,t,en,rst : in std_logic;
        Q: out std_logic;
        Qnot : out std_logic);
end T_flip_flop;
architecture TFF_arch of T_flip_flop is
signal op: std_logic;
begin
   process(clk, rst) is
    begin
      if(en=’0′) then op<=’Z’;
      elsif (en=’1′ and rst=’1′) then
          op <= ‘0’;
      elsif (clk’event and clk=’1′ and en=’1′) then
          if(t=’1′) then op <= not op;
          else op <= op;
          end if;
     end if;
end process;
Q <= op;
Qnot <= not op;
end TFF_arch;

To refresh your memory about how this works, go through the first two VHDL tutorials (1 and 2) of this series.

Next, compile the above program, creating and then saving a waveform file with all of the necessary inputs and outputs that are listed (and be sure to apply all of the different input combinations). Then, simulate the project. You should get the following result…

As shown in this figure, three cases are highlighted in red, blue, and green.

Case 1: when en=0 -> both outputs are at a high impedance
Case 2: when en=1 and rst=1 -> Q=0 and Qnot = 1 (the flip-flop is reset)
Case 3: when en=1, rst=0 and clk=1 and T=1 – > Q = 1 and Qnot = 0 (the output toggles between 0-1)

Be sure to verify the different input-output combinations as per the circuit’s truth table.

In the next tutorial, we’ll learn how to build a 4-bit binary counter using VHDL.