How to design half and full-subtractor circuits in Verilog

Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial. Follow the full series here.

In the previous Verilog Tutorial – 10, we designed half and full-adder circuits in Verilog.

In this tutorial, we’ll:

Write a Verilog program that builds half and full-subtractor circuits
Verify the output waveform of the program (the digital circuit) with truth tables for the half and full-subtractor circuits

Half-subtractor circuit

Truth table

Next, let’s write the VHDL program, compile and simulate it, and get the output in a waveform. We’ll also verify the output waveforms with the given truth table.

First, it’s important to review the step-by-step procedure provided in VHDL Tutorial – 3. In that tutorial, we learn how to design a project, edit and compile a program, create a waveform file, simulate the program, and generate the final output waveforms.

VHDL program

Gate-level modeling:

module half_sub(a,b,bo,dif);
input a,b;
output bo,dif;
wire a_not;

   not(a_not,a);
   xor(dif,a,b);
   and(bo,a_not,b);
endmodule;

Dataflow modeling:

module half_sub(a,b,bo,dif);
input a,b;
output bo,dif;

assign dif = a ^ b;
assign bo = ~a & b;
endmodule

Now, compile the above program, creating a waveform file with all of the necessary inputs and outputs that are listed, and simulate the project.

Here are the results…

Waveform simulation

Be sure to verify the ‘dif’ and ‘bo’ output waveforms with the given truth table. For the ‘a=1’ and ‘b=0’ inputs, the outputs are ‘bo=0’ and ‘dif=1,’ as highlighted in the above figure.

Next, let’s move on to the full-subtractor-circuit design.

Full-subtractor circuit

Truth table

Verilog program

Gate-level modeling:

module full_sub(a,b,bin,dif,bout);
input a,b,bin;
output dif,bout;
wire a_not,t1,t1_not,t2,t3;

xor(t1,a,b)
not(a_not,a);
not(t1_not,t1);
and(t2,a_not,b);
and(t3,t1_not,bin);
or(bout,t2,t3);
endmodule

Dataflow modeling:

module full_sub(a,b,bin,dif,bout);
input a,b,bin;
output dif,bout;

assign dif = a ^ b ^ bin;
assign bout = ~a & (b ^ bin) | b & bin;
endmodule

Let’s now explore the same program using a different modeling style: structural modeling. We previously used this approach in the full adder circuit tutorial.

In structural modeling, the complete program is divided into smaller, reusable modules. In this example, we’ll first create a module for a half subtractor, then use it twice. This process is called module instantiation. You can instantiate a complete Verilog module within any other Verilog program — this modularity is a key strength of Verilog.

This modeling style is especially useful when building large and complex Verilog designs, as it allows you to break down the overall program into manageable submodules. These modules can then be instantiated wherever needed in the main Verilog program.

Now, let’s see how to perform module instantiation in a Verilog program.

//////////// Verilog module of half subtractor ///////////////

module half_sub(a,b,dif,bor);
input a,b;
output dif,bor;
wire a_not;
xor(dif,a,b);
not(a_not,a);
and(bor,a_not,b);
endmodule

////// Verilog main program of full subtractor /////////////

module full_sub(a,b,bin,dif,bout);
input a,b,bin;
output dif,bout;
wire w1,w2,w3;
half_sub HS1(a,b,w1,w2); // module instantiation
half_sub HS2(w1,bin,dif,w3);
or(bout,w2,w3);
endmodule

Compile the above program, creating a waveform file with all of the listed inputs and outputs, and save the waveform file. Lastly, simulate the project and you should get following result.