How to compile, simulate, and verify a Verilog program using MAX+II-Part 3

In the previous two tutorials, we covered the basics of Verilog and explored several example programs using different modeling styles. In this tutorial, we will focus on how to simulate and verify Verilog programs.

To edit, compile, execute (simulate), or verify a Verilog program, you will need a software tool like Xilinx’s ISE, Mentor Graphics’ ModelSim, Aldec’s Riviera, or Altera’s Quartus-II, among others. These are commercial simulators. For this tutorial, we will use Altera’s MAX+II, a VHDL simulator particularly suited for educators and students.

Follow these step-by-step instructions to build and simulate a Verilog program for any digital circuit using MAX+II:

Step 1. Launch the MAX+II software from the Start menu. The following screen will appear on your computer.

Step 2. Create a file (File Menu → New) and a new dialog box will open. Select text editor file and click OK.

This will open the text editor where you can write our Verilog program.

Step 3. Let’s begin with a simple half-adder program.

module half_adder(a,b,sum,carry);
  input a,b;
  output sum,carry;
    xor(sum,a,b);
    and(carry,a,b);
endmodule

Write this code in the editor area and save it

Step 4. To save the program, click the save button (or go to File → Save). A save dialog box will appear. Select the appropriate directory and folder (e.g., E:\verilog_programs\half_adder).

It’s recommended to create a new folder for each Verilog program. Also, avoid using spaces (” “) in the complete path of the program. Name the file the same as the module name, “half_adder,” and choose the .v extension. Refer to the following figure for guidance.

Once saved, you’ll see all of the keywords, such as “module,” “endmodule,” etc., are highlighted.

Step 5. Now, let’s set this to an active project. Go to File → Project. Set the project to the current file.

Note that MAX+PLUS II automatically sets the project name to match the current file. In this case, it’s half_adder.

Step 6. Compile the file by navigating to MAX+PLUS II → Compiler. The compiler window will appear. Press the Start button to initiate the compilation process.

When the compilation is complete, it shows “0” errors and “0” warnings. Click OK to finish the compilation.

Step 7. Next, we must create a waveform editor file to visualize the input and output waveforms. This displays the simulation results.

To create the waveform editor file, go to MAX+PLUS II → Waveform Editor.

The following waveform editor window should open.

Step 8. Right-click on the blank area. From the pop-up menu, select “enter node from SNF.”

A new dialog box will appear. First, select List, then click the ‘⇒’ button. Press OK to confirm your selection.

You’ll see all of the input and output signal waveforms (“a,” “b,” “sum,” and “carry”) appearing on the waveform editor window.

Here, the “xx” lines indicate the output signals, which cannot be edited. However, it’s possible to edit the “a” and “b” input signals.

Step 9. Zoom out of the waveform by pressing the minimizer icon (labeled “Zoom out” below) on left-hand side.

Enter the values “a” and “b” as “1” and “0” by selecting the appropriate areas (press and hold your mouse button to select). You can elect the values “1” or “0” from the let-hand side.

Set the “1” or “0” values of “a” and “b” as desired. Then, make all four combinations “00,” “01,” “10,” and “11” as shown here.

Step 10. Save the waveform file. By default, its name is “half_adder.swf”. Click OK.

Step 11. For the simulatation, go to MAX+II → Simulator.

 

Click Start on the simulator dialogue box. The dialogue box appears as “0” errors and “0” warnings if the simulation is successful.

Step 12. Click OK, and then open the wavefrom editor file to verify the result of the half-adder.

This is the step-by-step procedure to edit, compile, simulate, and verify any Verilog program.

In the upcoming tutorials, we’ll focus on simulating various digital circuits in Verilog using MAX+PLUS II.

 

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Filed Under: Tutorials
Tagged With: max+II, simulate, software, tutorial, verilog
 

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