{"id":83117,"date":"2025-06-05T23:50:04","date_gmt":"2025-06-06T03:50:04","guid":{"rendered":"https:\/\/www.engineersgarage.com\/?p=83117"},"modified":"2025-06-10T17:42:42","modified_gmt":"2025-06-10T21:42:42","slug":"verilog-tutorial-13-how-to-design-a-3x8-decoder-and-an-8x3-encoder-in-vhdl","status":"publish","type":"post","link":"https:\/\/www.engineersgarage.com\/verilog-tutorial-13-how-to-design-a-3x8-decoder-and-an-8x3-encoder-in-vhdl\/","title":{"rendered":"Verilog Tutorial 13: How to design a 3\u00d78 decoder and an 8\u00d73 encoder in VHDL"},"content":{"rendered":"

Note: it\u2019s recommended to follow this VHDL tutorial series in order, starting with the\u00a0<\/em>first tutorial<\/em><\/a><\/strong>. Follow the full series\u00a0here<\/a>.<\/strong><\/em><\/p>\n

In the previous\u00a0Verilog Tutorial \u2013 12<\/strong><\/a>, we learned how to design half and full-subtractor circuits in Verilog.<\/p>\n

In this tutorial, we\u2019ll:<\/p>\n

    \n
  1. Write a Verilog program for building circuits for a 3\u00d78 decoder and an 8\u00d73 encoder<\/li>\n
  2. Verify the output waveform of the program (digital circuit) with the given truth tables for the encoder and decoder circuits<\/li>\n<\/ol>\n

    The 3\u00d78 decoder circuit:<\/strong><\/h3>\n

    \"\"<\/a><\/p>\n

    Truth table<\/h3>\n

    \"\"<\/a><\/p>\n

    Next, let\u2019s write the\u00a0Verilog\u00a0program, compile and simulate it, and get the output in a waveform. We\u2019ll also verify the output waveforms with the given truth table.<\/p>\n

    First, it\u2019s important to review the step-by-step procedure provided in\u00a0VHDL Tutorial \u2013 3<\/a><\/strong>. In that tutorial, we learn how to design a project, edit and compile a program, create a waveform file, simulate the program, and generate the final output waveforms.<\/span><\/p>\n

    Verilog program<\/span><\/strong><\/h3>\n

    Gate-level modeling:<\/strong><\/p>\n

    module decoder3x8(a,b,c,d);<\/strong><\/span>
    \n\u00a0 input a,b,c;<\/strong><\/span>
    \n\u00a0\u00a0 output [0:7] d;<\/strong><\/span>
    \n\u00a0\u00a0 wire a_not,b_not,c_not;<\/strong><\/span>
    \n\u00a0\u00a0 \u00a0 not(a_not,a);<\/strong><\/span>
    \n\u00a0\u00a0 \u00a0 not(b_not,b);<\/strong><\/span>
    \n\u00a0\u00a0 \u00a0 not(c_not,c);<\/strong><\/span>
    \n\u00a0\u00a0 \u00a0 and(d[0],a_not,b_not,c_not);<\/strong><\/span>
    \n\u00a0\u00a0 \u00a0 and(d[1],a,b_not,c_not);<\/strong><\/span>
    \nand(d[2],a_not,b,c_not);<\/strong><\/span>
    \n\u00a0\u00a0 \u00a0 and(d[3],a,b,c_not);<\/strong><\/span>
    \n\u00a0\u00a0\u00a0\u00a0 and(d[4],a_not,b_not,c);<\/strong><\/span>
    \n\u00a0\u00a0\u00a0\u00a0 and(d[5],a,b_not,c);<\/strong><\/span>
    \n\u00a0\u00a0\u00a0\u00a0 and(d[6],a_not,b,c);<\/strong><\/span>
    \n\u00a0\u00a0\u00a0\u00a0 and(d[7],a,b,c);<\/strong><\/span>
    \n\u00a0\u00a0 endmodule<\/strong><\/span><\/p>\n

    Dataflow modeling:<\/strong><\/p>\n

    \u00a0module decoder3x8(a,b,c,d);<\/strong><\/span>
    \n\u00a0 input a,b,c;<\/strong><\/span>
    \n\u00a0 output [0:7] d;<\/strong><\/span>
    \n\u00a0\u00a0\u00a0\u00a0 assign d[0] = ~a & ~b & ~c;<\/strong><\/span>
    \n\u00a0\u00a0\u00a0\u00a0 assign d[1] = a & ~b & ~c;<\/strong><\/span>
    \n\u00a0\u00a0\u00a0\u00a0 assign d[2] = ~a & b & ~c;<\/strong><\/span>
    \n\u00a0\u00a0\u00a0\u00a0 assign d[3] = a & b & ~c;<\/strong><\/span>
    \n\u00a0\u00a0\u00a0\u00a0 assign d[4] = ~a & ~b & c;<\/strong><\/span>
    \n\u00a0\u00a0\u00a0\u00a0 assign d[5] = a & ~b & c;<\/strong><\/span>
    \n\u00a0\u00a0\u00a0\u00a0 assign d[6] = ~a & b & c;<\/strong><\/span>
    \nassign d[7] = a & b & c;<\/strong><\/span>
    \n\u00a0 endmodule<\/strong><\/span><\/p>\n

    Now, compile the above program, creating a waveform file with all of the necessary inputs and outputs that are listed, and simulate the project.\u00a0<\/span><\/p>\n

    Here are the results\u2026<\/span><\/p>\n

    Waveform simulation<\/h3>\n

    \"\"<\/a><\/u><\/strong><\/p>\n

    Be sure to verify the D0-D7 output. You’ll note that only one output is high at a time. All of the others are then low, as per the given input A0-A1-A2 combinations from ‘000’ to ‘111.’<\/p>\n

    Next, let’s build the 8×3 encoder circuit.<\/p>\n

    The 8×3 encoder circuit:<\/strong><\/h3>\n

    \"\"<\/a><\/p>\n

    Truth table<\/strong><\/h3>\n

    \"\"<\/a><\/h3>\n

    Verilog program<\/strong><\/h3>\n

    Gate-level modeling:<\/strong><\/p>\n

    module encoder8x3(a,b,c,d);<\/strong><\/span>
    \n\u00a0 input [0:7] d;<\/strong><\/span>
    \n\u00a0 output a,b,c;<\/strong><\/span>
    \n\u00a0\u00a0\u00a0\u00a0 or(c, d[1], d[3], d[5], d[7]);<\/strong><\/span>
    \n\u00a0\u00a0\u00a0\u00a0 or(b, d[2], d[3], d[6], d[7]);<\/strong><\/span>
    \n\u00a0\u00a0\u00a0\u00a0 or(a, d[4], d[5], d[6], d[7]);<\/strong><\/span>
    \nendmodule<\/strong><\/span><\/p>\n

    Dataflow modeling<\/strong><\/p>\n

    module encoder8x3(a,b,c,d);<\/strong><\/span>
    \n\u00a0 input [0:7] d;<\/strong><\/span>
    \n\u00a0 output a,b,c;<\/strong><\/span>
    \n\u00a0\u00a0\u00a0\u00a0 assign c = d[1] | d[3] | d[5] | d[7]);<\/strong><\/span>
    \n\u00a0\u00a0\u00a0\u00a0 assign b = d[2] | d[3] | d[6] | d[7]);<\/strong><\/span>
    \n\u00a0\u00a0\u00a0\u00a0 assign a = d[4] | d[5] | d[6] | d[7]);<\/strong><\/span>
    \nendmodule<\/strong><\/span><\/p>\n

    Simulation waveforms<\/strong><\/h3>\n

    \"\"<\/a><\/p>\n

    As shown above, the input output waveforms looks similar to those of the decoder. This is because the encoder is simply the reverse of the decoder. So the input becomes output, and vice versa.<\/p>\n

    In the encoder example, when D7’s input is \u20181,\u2019 the outputs are ‘a = 1,’ ‘b=1,’ and ‘c=1.’ You can verify other combinations based on the truth table.<\/p>\n

    In next tutorial<\/a>, we’ll design circuits for an 8\u00d71 multiplexer and a 1\u00d78 de-multiplexer by using Verilog.<\/em><\/p>\n

     <\/p>\n","protected":false},"excerpt":{"rendered":"

    Note: it\u2019s recommended to follow this VHDL tutorial series in order, starting with the\u00a0first tutorial. Follow the full series\u00a0here. In the previous\u00a0Verilog Tutorial \u2013 12, we learned how to design half and full-subtractor circuits in Verilog. In this tutorial, we\u2019ll: Write a Verilog program for building circuits for a 3\u00d78 decoder and an 8\u00d73 encoder…<\/p>\n","protected":false},"author":64,"featured_media":83125,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_genesis_hide_title":false,"_genesis_hide_breadcrumbs":false,"_genesis_hide_singular_image":false,"_genesis_hide_footer_widgets":false,"_genesis_custom_body_class":"","_genesis_custom_post_class":"","_genesis_layout":"","footnotes":""},"categories":[9],"tags":[429,239,3338,4288,4534,2192],"class_list":{"2":"type-post","14":"entry","15":"has-post-thumbnail"},"acf":[],"yoast_head":"\nHow-to-design-a-3x8-decoder-and-an-8x3-encoder-in-vhdl<\/title>\n<meta name=\"description\" content=\"Master Verilog in this tutorial! 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