{"id":83141,"date":"2025-06-10T23:50:15","date_gmt":"2025-06-11T03:50:15","guid":{"rendered":"https:\/\/www.engineersgarage.com\/?p=83141"},"modified":"2025-06-10T17:38:51","modified_gmt":"2025-06-10T21:38:51","slug":"verilog-tutorial-15-how-to-design-a-clocked-sr-latch-in-verilog","status":"publish","type":"post","link":"https:\/\/www.engineersgarage.com\/verilog-tutorial-15-how-to-design-a-clocked-sr-latch-in-verilog\/","title":{"rendered":"Verilog Tutorial 15: How to design a clocked SR latch in Verilog"},"content":{"rendered":"

Note: it\u2019s recommended to follow this VHDL tutorial series in order, starting with the\u00a0<\/em>first tutorial<\/em><\/a><\/strong>. Follow the full series\u00a0here<\/a>.<\/strong><\/em><\/p>\n

In the previous\u00a0Verilog Tutorial \u2013 14<\/strong><\/a>, we learned how to design circuits for a 1×8 demultiplexer and an 8×1 multiplexer in Verilog.<\/p>\n

In this tutorial, we\u2019ll:<\/p>\n

    \n
  1. Write a Verilog program to build a clocked SR latch (flip-flop) circuit<\/li>\n
  2. Verify the output waveform of the program (digital circuit) with the truth table of the flip-flop circuit<\/li>\n<\/ol>\n

    Clocked SR latch circuit<\/strong><\/h3>\n

    \"\"<\/a><\/p>\n

    Truth table<\/h3>\n

    \"\"<\/a><\/p>\n

    Next, let\u2019s write the Verilog program, compile and simulate it, and get the output in a waveform. We\u2019ll also verify the output waveforms with the given truth table.<\/p>\n

    First, it\u2019s important to review the step-by-step procedure provided in\u00a0VHDL Tutorial \u2013 3<\/a><\/strong>. In that tutorial, we learn how to design a project, edit and compile a program, create a waveform file, simulate the program, and generate the final output waveforms.<\/span><\/p>\n

    Verilog program<\/span><\/strong><\/h3>\n

    Gate-level modeling:<\/strong><\/p>\n

    module srff_gate(q, qbar, s, r, clk);<\/strong><\/span><\/p>\n

    input s,r,clk;<\/strong><\/span>
    \noutput reg q, qbar;<\/strong><\/span><\/p>\n

    wire t1,t2;<\/strong><\/span><\/p>\n

    nand (t1,clk,s);<\/strong><\/span>
    \nnand (t2,clk,r);<\/strong><\/span>
    \nnor (q,t1,qbar);<\/strong><\/span>
    \nnor (qbar,t2,q);<\/strong><\/span><\/p>\n

    endmodule<\/strong><\/span><\/p>\n

    Behavioral modeling:<\/strong><\/p>\n

    module srff_behave(s,r,clk, q, qbar);<\/strong><\/span><\/p>\n

    input s,r,clk;<\/strong><\/span>
    \noutput q, qbar;<\/strong><\/span>
    \nreg q, qbar;<\/strong><\/span>
    \n\u00a0always@(posedge clk)<\/strong><\/span>
    \n\u00a0 begin<\/strong><\/span><\/p>\n

    if(s == 1)<\/strong><\/span>
    \n\u00a0begin<\/strong><\/span>
    \nq = 1;<\/strong><\/span>
    \nqbar = 0;<\/strong><\/span>
    \nend<\/strong><\/span>
    \nelse if(r == 1)<\/strong><\/span>
    \n\u00a0begin<\/strong><\/span>
    \nq = 0;<\/strong><\/span>
    \nqbar =1;<\/strong><\/span>
    \n\u00a0end<\/strong><\/span>
    \nelse if(s == 0 & r == 0)<\/strong><\/span>
    \n\u00a0begin<\/strong><\/span>
    \nq <= q;<\/strong><\/span>
    \nqbar <= qbar<\/strong><\/span>
    \n\u00a0end<\/strong><\/span>
    \n\u00a0end<\/strong><\/span>
    \nendmodule<\/strong><\/span><\/p>\n

    Now, compile the above program, creating a waveform file with all of the necessary inputs and outputs that are listed, and simulate the project.\u00a0<\/span><\/p>\n

    Here are the results\u2026<\/span><\/p>\n

    Waveform simulation<\/h3>\n

    \"\"<\/a><\/p>\n

    As shown above, when the clock input is \u20181\u2019, then “s” is \u20181.’ When “r” is \u20180,\u2019 the flip-flop is set, meaning the output for “Q” is \u20181\u2019 and for “Qnot” it’s \u20180.\u2019 You can verify other combinations using the given in truth table.<\/p>\n

    in next tutorial, we’ll learn how to design a “D” flip-flop using Verilog.<\/em><\/p>\n

     <\/p>\n

     <\/p>\n","protected":false},"excerpt":{"rendered":"

    Note: it\u2019s recommended to follow this VHDL tutorial series in order, starting with the\u00a0first tutorial. Follow the full series\u00a0here. In the previous\u00a0Verilog Tutorial \u2013 14, we learned how to design circuits for a 1×8 demultiplexer and an 8×1 multiplexer in Verilog. In this tutorial, we\u2019ll: Write a Verilog program to build a clocked SR latch…<\/p>\n","protected":false},"author":64,"featured_media":83146,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_genesis_hide_title":false,"_genesis_hide_breadcrumbs":false,"_genesis_hide_singular_image":false,"_genesis_hide_footer_widgets":false,"_genesis_custom_body_class":"","_genesis_custom_post_class":"","_genesis_layout":"","footnotes":""},"categories":[9],"tags":[47,4696,4288,4534,1246],"class_list":{"2":"type-post","13":"entry","14":"has-post-thumbnail"},"acf":[],"yoast_head":"\nHow-to-design-a-clocked-sr-latch-in-verilog<\/title>\n<meta name=\"description\" content=\"Learn how to write a Verilog program to create a clocked SR latch and verify it with waveforms and truth tables.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link 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