How-to-design-a-clocked-sr-latch-in-verilog

Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial. Follow the full series here.

In the previous Verilog Tutorial – 14, we learned how to design circuits for a 1×8 demultiplexer and an 8×1 multiplexer in Verilog.

In this tutorial, we’ll:

Write a Verilog program to build a clocked SR latch (flip-flop) circuit
Verify the output waveform of the program (digital circuit) with the truth table of the flip-flop circuit

Clocked SR latch circuit

Truth table

Next, let’s write the Verilog program, compile and simulate it, and get the output in a waveform. We’ll also verify the output waveforms with the given truth table.

First, it’s important to review the step-by-step procedure provided in VHDL Tutorial – 3. In that tutorial, we learn how to design a project, edit and compile a program, create a waveform file, simulate the program, and generate the final output waveforms.

Verilog program

Gate-level modeling:

module srff_gate(q, qbar, s, r, clk);

input s,r,clk;
output reg q, qbar;

wire t1,t2;

nand (t1,clk,s);
nand (t2,clk,r);
nor (q,t1,qbar);
nor (qbar,t2,q);

endmodule

Behavioral modeling:

module srff_behave(s,r,clk, q, qbar);

input s,r,clk;
output q, qbar;
reg q, qbar;
always@(posedge clk)
begin

if(s == 1)
begin
q = 1;
qbar = 0;
end
else if(r == 1)
begin
q = 0;
qbar =1;
end
else if(s == 0 & r == 0)
begin
q <= q;
qbar <= qbar
end
end
endmodule

Now, compile the above program, creating a waveform file with all of the necessary inputs and outputs that are listed, and simulate the project.

Here are the results…

Waveform simulation

As shown above, when the clock input is ‘1’, then “s” is ‘1.’ When “r” is ‘0,’ the flip-flop is set, meaning the output for “Q” is ‘1’ and for “Qnot” it’s ‘0.’ You can verify other combinations using the given in truth table.

in next tutorial, we’ll learn how to design a “D” flip-flop using Verilog.